A fin field-effect transistor and a method for fabricating such a fin field-effect transistor are described in D. Hisamoto et al., A Fully Depleted Lean-Channel Transistor (DELTA)—A novel vertical ultrathin SOI MOSFET, IEEE Electron Device Letters, Volume 11, No. 1, pages 36-38, 1990 (hereinafter Hisamoto 1990.) FIG. 2 shows such a fin field-effect transistor 200 having a silicon substrate 201 and an oxide layer 202 made of silicon oxide SiO2 on the silicon susbtrate 201.
A fin 203 made of silicon is provided on a part of the oxide layer 202. A gate 204 of the resulting fin field-effect transistor 200 is arranged above a part of the fin 203 and along the entire height of the part of the fin.
In the case of the fin field-effect transistor 200 described in Hisamoto 1990, the channel region, not visible in the figure, of the fin 203 can be inverted by charge carriers with the aid of the gate 204 extending along the side walls 205 of the fin 203. The fin 203, which is also referred to as a Mesa, has on its end sections a source region 206 and a drain region 207.
In the case of the fin field-effect transistor 200 described in Hisamoto 1990, there is no self-aligned spacer technology for the LDD implantation or HDD implantation, in order that the fin 203 is not highly doped with doping atoms in the source region 206 and in the drain region 207 until after the application of the gate, and that an overlapping of the gate and the source or drain region, and a disadvantageous control response, associated therewith in turn, of the transistor is avoided.
In the case of the fin field-effect, transistor 200 described in Hisamoto 1990, there are firstly formed along the side walls 205 of the fin 203 oxide spacers 208 which prevent a doping of the fin 203 by implantation via the side walls 205. In the case of implantation via the free fin surfaces, however, in addition to the source region 206 and the drain region 207, the channel region that is not protected by oxide spacers is provided with doping atoms. In the case of this underdiffusion, doping atoms pass laterally into the channel region after their implantation. Particularly in the case of short channel lengths—such as occur in the case of the known fin field-effect transistor—such underdiffusion has substantial negative effects on the control response of the field-effect transistor.
Furthermore, there is described in D. Hisamoto et al., A folded-channel MOSFET for deep-sub-tenth micron era, IEDM 98, pages 1032-1034, 1998 (hereinafter Hisamoto 1998) a fin field-effect transistor in the case of which the silicon fin is fed through in the horizontal direction by the electric current to be controlled. In the fabrication method in accordance with Hisamoto 1998, the highly doped source/drain regions are already present when the gate oxide made of silicon dioxide is grown on. This leads to a substantial running of the dopant and to undesired series resistances, particularly in the case of a very short channel.
J. Kedzierski et al., Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime, IEDM 2000, pages 57-60, describes a MOS field-effect transistor in the case of which the drain region and the source region are formed from platinum silicide.
U.S. Pat. No. 6,252,284 B1 describes a planarized fin field-effect transistor in the case of which a spacer is arranged as electrical insulation layer between source and gate and between drain and gate, respectively, in each case between source and gate and between drain and gate.
Furthermore, U.S. Pat. No. 5,300,455 A describes a method for fabricating an electrically conductive diffusion barrier at the metal/silicon interface of an MOS field-effect transistor.
U.S. Pat. No. 6,207,511 B1 describes a transistor having one or more strip channels and in the case of which the current flow takes place in the lateral direction between source and drain. The gate is located at the side walls and, if required, on the strip channel or channels.
U.S. Pat. No. 5,623,155 A describes an SOI-MOS field-effect transistor.
U.S. Pat. No. 4,996,574 A describes an MIS transistor structure for increasing the conductivity between source and drain.